1. Field of the Invention
The invention relates to data processing systems and more particularly to addressing apparatus for interrupting a computer program utilizing an interrupt vector which can provide the addresses of 64 unique function codes for directing the execution of any of 64 interrupt routines.
2. Description of Prior Art
In running a computer program there are in general two phases which normally alternate. First, instructions and/or operands are fetched to the central processor and then the instructions are executed. During the fetch phase, the processor fetches the next instruction to be executed from main memory, and it to one or more control registers where such further modifications for indexing, indirect addressing, and base addition as required may be performed. During the execution phase of an instruction, the processor decodes the instruction and the operation specified by the instruction is executed.
Most stored program digital computers have some means of interrupting the running program upon request either from an external or internal signal. There are a variety of reasons why it is necessary to interrupt a computer program, such as for input or output of information or for calling some routine for performing a standard routine such as maintenance, diagnostic, square-root, etc.
The simplest form of interrupt is to utilize an instruction which causes a halt or branch, such as a HALT or a GO TO, and RETURN subroutine which causes the CPU to go to another location in main memory to obtain the next instruction to be executed rather than continuing with the next sequential instruction of the program. However, before executing the new program or routine, the contents of any indirectly addressable registers such as program counters, accumulator registers or the like must be preserved so that control may be returned to the interrupted program at the point where it was interrupted. This entails additional time in unloading and reloading the program counter.
There are many variations to this basic interrupt function such as conditional interrupts, priority interrupts, and nested interrupts. See the following U.S. Pat. Nos. for typical prior art interrupts:
(1) Interrupt System, by H. D. Wise, having U.S. Pat. No. 3,226,694, issued Dec. 28, 1965.
(2) Digital Computer Having High Speed Branch Operation, by R. E. Packard, et al, having U.S. Pat. No. 3,408,630, issued Oct. 29, 1968.
(3) Priority Interrupt Monitoring System, by Ralph Benghiat, having U.S. Pat. No. 3,221,309, issued Nov. 30, 1965.
(4) Subroutine Call and Return Means for an Electronic Calculator, by Richard M. Spangles, having U.S. Pat. No. 3,693,162, issued Sept. 19, 1972.
(The above references are exemplary only and no inference should be drawn that this is the closest prior art to the invention.)
Generally, both instructions and data operands are stored for execution in various addressable locations in the same main memory. Moreover, the instructions may be further grouped in groups forming subroutines. This requires that address locations be assigned in advance when the program of a subroutine for a particular problem is computed. Moreover, if the subroutine is later modified, the programmer must keep track not only of the original allocations of memory but also of the later modifications. In order to make programming independent of the actual address locations in main memory, indirect addressing has been resorted to. By means of index registers, groups of data or programs may be used without assigning specific address locations to each word in the group at the time the program is compiled. Although the absolute address is later inserted in the memory location referred to by the command, it can be different each time the program is run, depending on where the group is placed by the executing program in main memory. Since the group may be indirectly addressable by a number of commands, the address of the commands remains unchanged and only the absolute address of the group is changed if the location of the group is modified. This technique generally requires special words known as descriptions in place of operand words or instruction words in memory. When an instruction causes an operand word to be read out of memory, it may find a data descriptor word which includes a base address of a group of words. This further includes information identifying it as a descriptor word instead of an operand word, information as to the length of the group of instructions or data, and information indicating whether or not indexing is required.
(See U.S. Pat. No. 3,938,096, issued Feb. 10, 1976, entitled "Apparatus for Developing an Address of a Segment Within Main Memory and an Absolute Address of an Operand Within the Segment"; see also U.S. Pat. No. 3,222,649, issued Dec. 7, 1965, entitled "Digital Computer With Indirect Addressing". )
Whereas it is desirable in an interrupt operation to have operands or instructions grouped in groups which may be placed anywhere in main memory, it is just as desirable that the addresses of the descriptors or other type indirect address words be fixed. This may be done by having a central location such as a segment or a table for storing such words. Both of these techniques are comparatively slow; one requires several accesses of main memory to access descriptors by indirection, whereas the other requires comparison of the command or function code word to the words stored in the table. Moreover, these techniques require substantial amounts of memory space. Where a microprocessor is used, such storage space and speed are at a premium. Accordingly, a hardware technique of interrupt by indirection to any one of several predetermined locations is needed which is fast and is miserly in the utilization of processor and main memory storage.